Manufacturers of semiconductor integrated circuits have been experimenting with the use of copper to form the interconnect metallization upon integrated circuits. Copper has much better conductivity than the traditional aluminum metallization that has been used in past years, and improved conductivity is essential to achieve higher speed operation.
Such integrated circuits typically have a series of electrical connection pads by which the integrated circuit can be electrically joined with other external circuitry. For example, wire bonds have long been used to electrically couple the connection pads of an integrated circuit to the leads of a package, or to a supporting substrate. Solder bumps are also a cost-effective, and convenient, method of electrically coupling integrated circuits to supporting substrates within an electronics system; such solder bumps are often formed on integrated circuit wafers of the type that are used in providing so-called flip chip integrated circuit packages and/or chip scale packages.
Traditional wire bond and solder bumping methods cannot be used reliably with integrated circuits using copper interconnect metallization. In the case of gold wire bonds, an interaction takes place between the gold of the gold wire bond and the very thin copper layer to which it is bonded, and this interaction degrades the performance and reliability of the copper layer. Likewise, in the case of solder balls, an interaction takes place between the Sn/Pb solder and the very thin copper layer to which the solder is applied, and this interaction similarly degrades the performance and reliability of the copper layer. In addition, solder bumps require a solder diffusion barrier between the solder and the final copper metal of the integrated circuit. Others have proposed the use of nickel to serve as a bridge and barrier between the copper and gold in various applications. However, in many cases, integrated circuit die must be thermal cycled either at the wafer level (i.e., prior to scribing the die), or at the individual die level (after the wafer is scribed and the die are xe2x80x9cbrokenxe2x80x9d apart from the wafer), before the integrated circuit is finally assembled. Such thermal cycling steps could include wire bonding, die attachment, and wafer-level bum-in used to detect marginal Ics. In some cases, such thermal cycling is conducted in order to eliminate defects within, and improve the performance of, transistors and other devices formed within such integrated circuits, as by releasing trapped charges from the semiconductor devices (FETs, etc.) that are part of the integrated circuits. The heating associated with such thermal cycling tends to cause the nickel material to diffuse outwardly into the gold wire or solder bump, and such outward diffusion weakens the joint between the gold wire bond, or the solder bump, and the integrated circuit connection pad.
As is well known, integrated circuits are typically fabricated from semiconductor wafers in which a relatively large number of such identical integrated circuits are fabricated at once. Once the wafer level processing of such semiconductor wafers is complete, the wafers are scribed and broken along the scribe lines to form individual integrated circuit die. Clearly, it is an advantage to perform required processes at the wafer level, rather than at the individual circuit die level, as costs are thereby minimized.
Accordingly, it is an object of the present invention to provide an integrated circuit structure at the wafer level which makes use of copper interconnect metallization while facilitating the electrical coupling of connection pads of the integrated circuits to supporting substrates or other packaging.
Another object of the present invention is to provide such an integrated circuit structure using known metal deposition processes in a simple and inexpensive manner.
Still another object of the present invention is to provide such an integrated circuit structure which is compatible with gold wire bonds, solder bumps, and other common circuit connection methods.
A further object of the present invention is to provide such an integrated circuit structure capable of permitting relatively tight spacings between adjacent connection pads without compromising the reliability of the integrated circuit.
Yet another object of the present invention is to provide a process for forming connection pads on a plurality of integrated circuit die formed in semiconductor wafer, wherein the process is compatible with copper interconnect metallization while facilitating the use of gold wire bonds, solder bumps, and other common methods for electrically interconnecting the electrodes of an integrated circuit to a supporting substrate or packaging.
These and other objects of the present invention will become more apparent to those skilled in the art as the description of the present invention proceeds.
Briefly described, and in accordance with a preferred embodiment thereof, the present invention relates to an integrated circuit structure that includes a semiconductor wafer having a number of integrated circuit die formed therein, each having a series of semiconductor devices formed therein upon one surface of the semiconductor wafer. A patterned layer of interconnect metal, preferably formed of copper, is formed upon the upper surface of the semiconductor wafer for electrically interconnecting the various semiconductor devices formed within each such die. The patterned interconnect metal layer includes connection pads for making electrical connection to external circuitry. A patterned layer of nickel is plated, preferably by an electroless plating process, over each connection pad for mechanically and electrically bonding to the interconnect metal forming such connection pad. A patterned layer of palladium is then plated, preferably by an electroless plating process, over the previously-applied layer of nickel above each connection pad for preventing the nickel from out-diffusing during subsequent thermal cycling to a patterned gold layer that is applied over the palladium layer. Thereafter, the patterned layer of gold is plated, again preferably by an electroless plating process, over the patterned layer of palladium above each connection pad to facilitate the joinder of such connection pad with a connection element, such as a gold wire bond, solder bump, or the like. The intermediate palladium layer acts as a diffusion barrier, and prevents the underlying nickel from diffusing into the uppermost gold layer.
The integrated circuit structure described above can be used to form relatively tight geometries, i.e., connection pads can be formed relatively close to each other without jeopardizing the reliability of the resulting integrated circuits. For example, integrated circuit structures made in this manner permit two adjacent connection pads to be disposed within 5 micrometers, or less, of each other.
In the preferred embodiment of the present invention, the Ni/Pd/Au metallization stack may have a nickel layer thickness ranging between 0.5 micrometers and 20 micrometers; a palladium thickness ranging between 0.1 micrometers and 5 micrometers; and a gold layer thickness ranging between 0.03 micrometers and 2 micrometers.
Another aspect of the present invention relates to the process for forming such integrated circuit structure, and more particularly, to the process for forming the connection pads on the integrated circuit die during wafer level processing. The process includes the step of forming the patterned layer of interconnect metal upon a surface of the semiconductor wafer for electrically interconnecting the various semiconductor devices formed within each such integrated circuit die, as well as forming connection pads for making electrical connection to circuitry external to the semiconductor wafer. The process includes the step of forming a patterned layer of nickel by electroless plating over each connection pad for mechanically and electrically bonding to the interconnect metal at each such connection pad. Thereafter, the process forms a patterned layer of palladium by electroless plating over the patterned layer of nickel above each connection pad for preventing the nickel from out-diffusing through the palladium during subsequent heating cycles. Preferably, this palladium layer is plated directly onto the nickel layer without any intervening layer. A patterned layer of gold is then formed by electroless plating over the patterned layer of palladium above each connection pad to facilitate the joinder of such connection pad with a connection element, such as a solder bump or wire bond. This process permits connection pads to be disposed relatively closely to each other, e.g., within 5 micrometers of each other. If desired, the process may further include a thermal cycle heating step without causing the nickel layer to out-diffuse into the gold layer.